At IEEE Quantum Week 2026, many of the most important discussions went beyond the performance of individual quantum processors. From modular photonic architectures and hardware-aware compilation to logical computing and GPU–QPU integration, the conference offered a view of quantum computing becoming a complete infrastructure challenge. Quandela contributed to this discussion through three scientific presentations, two Best Paper distinctions and a joint NVIDIA–Quandela white paper outlining a practical path for bringing photonic QPUs into AI and high-performance computing workflows.
A quantum processing unit does not scale alone
For years, progress in quantum computing has often been communicated through individual device metrics: qubit counts, fidelities and circuit sizes. At IEEE Quantum Week 2026, held in Toronto from September 13 to 18, many of the more revealing questions were system-level ones. How do quantum modules connect? How should software account for imperfect hardware? How will logical computations be compiled and measured? And how can a quantum processing unit, or QPU, become part of the AI and high-performance computing infrastructure that organizations already operate?
Across the panels, papers and keynotes followed by the Quandela team, three themes stood out. Quandela contributed directly to each of them through work on scalable photonic architectures, photonic quantum machine learning and hardware-aware compilation. Two of the presented papers were ranked among the Best Papers in their respective tracks.
Scaling means connecting, not simply adding
A larger quantum computer is not necessarily a single, ever-growing processor. Many approaches to fault-tolerant quantum computing rely on modular architectures, in which smaller processing units are connected through quantum interconnects.
This was the focus of the panel Scaling Quantum Computing and Communication with Photon-Interfaced Spin Qubits, joined by Quandela’s Nicolas Maring. Hybrid matter–photon systems combine stationary qubits, which can store and process information locally, with photons, which can carry quantum information between modules. The approach creates a bridge between local processing, distributed quantum architectures and quantum communication networks.
Across the conference, discussions around modular photonic architectures repeatedly returned to the same constraint: as systems grow, interconnection losses and component performance become system-level challenges.
Useful performance depends on software that understands the hardware
The same movement toward co-design is visible in algorithms and compilation.
One Quandela paper examined trainability in photonic variational circuits. These circuits are adjusted during an optimization process, but their gradients can become extremely small, creating what researchers call a barren plateau. When this happens, finding better circuit parameters becomes increasingly difficult.
The study found that post-selection, the choice to retain only certain measurement outcomes, can materially affect gradient behaviour over the system sizes studied. Some post-selection configurations remained consistent with polynomial gradient scaling, while dual-rail post-selection moved toward exponential concentration beyond moderate sizes. The result provides a more precise basis for designing trainable photonic models, rather than assuming that all larger circuits will face the same optimization barrier.
The work received second place in the Quantum Machine Learning Best Paper ranking.
A second Quandela paper addressed compilation on real photonic processors. Instead of treating every optical component as identical, the proposed method selects where to place a subcircuit and how to route photons based on measured loss, phase noise and component performance.
Across the evaluated benchmarks, the method improved the coincidence rate, the probability of detecting all the photons required for the computation, by up to 33.2% compared with existing approaches. The work received third place in the Quantum Photonics Best Paper ranking.
The field is preparing to measure logical computation
Another signal was the shift from describing machines primarily through physical qubits toward evaluating the computations they can reliably execute.
The Quantum Universal Operations Performance System (QUOPS) reflects this evolution by measuring both the size of circuits a quantum system can execute successfully and the rate at which those computations can be performed. Designed to work across different hardware technologies, the framework can also extend from physical to logical qubits as fault-tolerant systems develop. arXiv
NVIDIA’s CUDA-Q Logical addresses the complementary software question: how to compile and analyze a fault-tolerant algorithm across different error-correction codes, decoders, execution models, hardware architectures and classical resources. Rather than relying only on top-level resource formulas, this approach makes it possible to study how routing, correction, decoding and classical communication contribute to the real execution cost.
For future users, this represents a meaningful change in language. The relevant question is not only how many qubits a machine contains, but what workload it can execute, with what reliability, throughput and resource overhead.
What this means for HPC centers and public institutions
For HPC centers, data centers, governments and research institutions, quantum readiness is therefore larger than a hardware procurement decision.
It also requires teams that can reproduce scientific results, compare quantum and classical methods, simulate workloads, understand architecture-specific constraints and integrate QPUs into existing software, security and governance environments. Institutions will need evidence that extends beyond headline hardware metrics.
This does not require assuming that every workload will benefit from quantum computing. It requires the ability to test that question rigorously. Organizations that build the necessary skills and interfaces can evaluate emerging systems against their own scientific and operational requirements, while preserving the infrastructure already supporting their users.
The next practical question: where does the QPU sit?
This systems perspective is the starting point of the joint NVIDIA × Quandela technical white paper, Bringing QPUs Into AI and HPC Workflows.
Presented during IEEE Quantum Week, the paper looks beyond access to quantum hardware and asks a more operational question: how can a photonic QPU become a usable computing resource inside the AI and HPC infrastructure organizations already rely on?
The value of this architecture is continuity. Teams can develop and simulate algorithms using GPU resources, test selected workloads on physical quantum hardware and compare the results within a more consistent environment.
For infrastructure operators, the objective is not to create a separate quantum data center. It is to make the QPU interoperable with the software, computing and orchestration layers already in place.
A staged path to quantum adoption
The white paper proposes three stages: Access, Integration & Discovery, and Scale.
Access enables organizations to experiment with quantum computing and build initial expertise without operating their own infrastructure.
Integration & Discovery brings the QPU into CPU and GPU environments so that teams can develop algorithms, compare simulation with hardware execution and identify workloads where quantum processing is technically relevant.
Scale applies to the smaller set of applications that demonstrate enough potential to justify more powerful quantum systems and deeper infrastructure integration. Quandela
This is a pragmatic model for quantum adoption. It gives institutions a way to prepare without making premature claims about quantum advantage or replacing existing investments. The immediate work is to build evidence, interoperability and operational knowledge so that credible applications can advance as the hardware matures.
Key Takeaways
- Scaling quantum computing increasingly requires progress across architecture, algorithms, compilation, error correction and classical integration.
- Quandela presented work across several of these layers, with papers ranked second in Quantum Machine Learning and third in Quantum Photonics.
- Selected IEEE sessions reflected a broader movement toward modular systems, architecture-aware software and logical-level benchmarks.
- The NVIDIA × Quandela white paper proposes a staged path for integrating photonic QPUs into existing AI and HPC workflows.
From devices to computing systems
IEEE Quantum Week 2026 offered a view of a field broadening its definition of progress. Better quantum devices remain essential, but they are only one part of the path toward useful computing. Architecture, algorithms, compilation, fault tolerance and classical integration increasingly have to advance together.
Quandela’s contributions in Toronto, and the architecture developed with NVIDIA, reflect that full-stack direction: rigorous science at the processor level, combined with a practical path for bringing photonic QPUs into future AI and HPC environments.
References
- IEEE Quantum Week 2026. Scaling Quantum Computing and Communication with Photon-Interfaced Spin Qubits. Panel program.
- Yichen Xie, Cassandre Notton and Jean Senellart. Pre-Asymptotic Trainability in Photonic Variational Circuits under Postselection. arXiv:2605.11879, 2026. arXiv
- Tobias Forster, Yannick Stade, Andreas Fyrillas, Jean Senellart, Lukas Burgholzer and Robert Wille. Handling Imperfections in Subcircuit Compilation for Linear Optical Quantum Computing. arXiv:2609.13379, 2026. arXiv
- Harriet Apel et al. Compiling the 2D Fermi-Hubbard Ground-State Energy Estimation Algorithm for Active Volume Quantum Architectures. arXiv:2609.05316, 2026. arXiv
- Timothy Proctor et al. Benchmarking the Computational Power of Quantum Computers. arXiv:2609.12146, 2026. arXiv
- NVIDIA. NVIDIA Expands Open Source CUDA-Q Platform for Fault-Tolerant Quantum Computing. September 2026. NVIDIA Newsroom